1. Field of the Invention
The present invention relates to an antifuse address detecting circuit and a semiconductor integrated circuit device, and particularly relates to a structure which uses antifuses and is programmable by applying a high voltage thereto.
2. Description of the Background Art
A semiconductor integrated circuit device provided with memory cells which are arranged in rows and columns to form an array is also provided with a spare row line and a spare column line, which will be also referred to as xe2x80x9credundant linesxe2x80x9d hereinafter. Owing to provision of a redundant structure, a defective memory cell or a defective line is repaired by substituting the redundant line for the defective memory cell or line. Provision of the redundant structure improves a rate of acceptable chips on a wafer.
This structure requires an internal circuit, in which a defective address is programmed in advance. In a practical operation, the internal circuit monitors the row and column addresses which are actually input, and can perform substitution of the spare line when it detects that a defective address is input.
For example, Journal of Solid State Circuit Vol. SC-18 (1983), pp. 441-446 (which will be referred to as a xe2x80x9creference 1xe2x80x9d hereinafter) has disclosed a fuse-bank address detecting circuit, which is an example of the above internal circuit.
An example of a structure of a conventional fuse-bank address detecting circuit 800 disclosed in the reference 1 will be described below with reference to FIG. 23. The conventional fuse-bank address detecting circuit 800 shown in FIG. 23 includes a plurality of fuses F11, F12, . . . , Fm1 and Fm2 as well as a plurality of transistors T11, T12, . . . , Tm1, Tm2 and Tx. Fuses F11-Fm2 which are program elements are connected to a common node Z. A fuse corresponding to a defective address is blown in advance. Thereby, the defective address is programmed (stored). A transistor Tx charges and thereby initializes common node Z in response to a precharge signal PR.
Transistors T11-Tm2 are arranged correspondingly to fuses F11-Fm2, respectively. Transistors T11, T12, . . . , Tm1 and Tm2 receive address signals a1, /a1, . . . , am and/am on their gates, respectively. A signal (inactivating signal fDA) on common node Z changes depending on matching and mismatching between the input address signal and the programmed defective address. A decoder (not shown) receiving this signal selects the redundant line instead of the defective line.
However, the conventional fuse-bank address detecting circuit 800 shown in FIG. 23 requires an expensive laser cutter device for blowing off the fuse. Also, a process load for blowing off the fuse is large, and further a variation occurs in accuracy of blowing.
In contrast to the foregoing, U.S. Pat. No. 5,631,862 (May 20, 1997), which will be referred to as a xe2x80x9creference 2xe2x80x9d hereinafter, has disclosed a structure of an antifuse address detecting circuit which does not use a fuse.
An antifuse program circuit 900 which is included in the conventional antifuse address detecting circuit disclosed in the reference 2 will be described below with reference to FIG. 24.
Antifuse program circuit 900 shown in FIG. 24 includes PMOS transistors P8, P9 and P10, NMOS transistors N11, N12, N13, N14 and N16, an inverter circuit 917 and an antifuse 901.
Antifuse 901 has a structure of a capacity type, and usually functions as an open circuit. However, by applying a high voltage thereto and thereby blowing the capacity type structure, it forms a conductive path having a resistance of about several kilohms.
NMOS transistor N16 and antifuse 901 are connected in series between nodes VCON and CGND. Node CGND is set to a level of a ground potential GND in a normal mode, and is supplied with a high voltage of 10 V or more when antifuse 901 is blown (i.e., in an address program mode).
NMOS transistor N16 operates such that a voltage higher than a breakdown voltage of a gate oxide film may not be applied across the sources and gates, or drains and gates of NMOS transistors N11, N12 and N13 when a high voltage of 10 V or more is applied to node CGND.
NMOS transistors N12, N13 and N14 are connected in series between the ground potentials. NMOS transistor N12 receives on its gate electrode a reset signal RST. Reset signal RST is active and at H-level when it is initially set. NMOS transistor N13 receives on its gate electrode an address signal ADDR.
NMOS transistor N14 receives on its gate electrode a signal FR which is an output of inverter circuit 917 (i.e., an output of this circuit). Signal FR is an input signal of an address comparing circuit (not shown), which is formed of an NOR logic gate or an NAND logic gate, and performs comparison of address signal ADDR. NMOS transistor N14 may be turned off with signal FR to interrupt a path of current, which tends to flow toward the ground potential via nodes VCOM and NMOS transistors N13 and N14 when blowing antifuse 901.
PMOS transistors P8 and P9 are connected between an internal power supply potential VCC and a node W. PMOS transistor P8 receives on its gate electrode a signal T(RAS). PMOS transistor P9 receives signal FR on its gate electrode.
PMOS transistor P10 and NMOS transistor N11 are connected in series between nodes W and VCOM. NMOS transistor N11 receives a signal DVCE on its gate electrode. Signal DVCE is an enable signal of this circuit, and its level is raised to half the internal power supply voltage (Vcc/2) when blowing antifuse 901 or detecting the address. PMOS transistor P10 has a channel length and a channel width which are determined to provide a channel resistance of about 300 Kxcexa9, and is always on.
NMOS transistor N11 has a channel length and a channel width which are determined to provide a current drive power exceeding that of PMOS transistor P10. Inverter circuit 917 is connected to a connection node between PMOS and NMOS transistors P10 and N11.
In the foregoing circuit, in which programming is performed with the antifuse not requiring laser for blowing, steps for laser blowing can be reduced. Also, an expensive device for blowing is not required.
However, the structure using the antifuse as a program element suffers from such a problem (erroneous programming) that serge (noises) entering an interconnection for voltage application blows an antifuse not requiring programming.
Further, an excessive current flows when the antifuse is blown, and it is necessary to suppress an influence exerted on peripheral elements by the excessive current.
If the antifuse is used as the program element, the antifuse for a defective address must be reliably blown. Even if the blowing is insufficient, a normal operation must be ensured. Further, it is necessary to verify an operation of the antifuse address detecting circuit, and it is also necessary to remove an initial failure in the program elements.
If the above structure is applied to a semiconductor integrated circuit device, it is necessary to reduce the number of circuit elements and therefore a layout area.
An object of the invention is to provide an antifuse address detecting circuit, overcoming the above problems, which uses an antifuse as a program element, and can suppress an influence, which may be exerted on its peripheral elements by blowing the same.
Another object of the invention is to provide an antifuse address detecting circuit, which uses an antifuse as a program element, and can stably and reliably blow the antifuse.
Still another object of the invention is to provide a semiconductor integrated circuit device, in which an antifuse address detecting circuit programmable by applying a high voltage is used as a redundancy determining circuit, and particularly a semiconductor integrated circuit device which can suppress an influence exerted by the high voltage on a peripheral circuit, and requires a small layout area.
Yet another object of the invention is to provide a semiconductor integrated circuit device, in which an antifuse address detecting circuit programmable by applying a high voltage is used as a redundancy determining circuit, and particularly a semiconductor integrated circuit device which can reliably perform redundancy determination.
An antifuse address detecting circuit according to the invention includes an antifuse having a capacity type structure, and changing into a low-resistance element when the capacity type structure is blown by application of a high voltage; a first node connected to one of terminals of the antifuse; a second node connected to the other terminal of the antifuse; a first supply circuit for supplying the high voltage required for blowing the antifuse to the first node in a program mode for blowing the antifuse; a second supply circuit for supplying a voltage to the second node; and a control circuit for controlling supply of the voltage from the first supply circuit to the first node in response to the voltage on the second node.
Accordingly, a major advantage of the invention is that programming can be performed easily with a high voltage. Also, an influence which may be exerted on a peripheral element by a high voltage can be prevented by controlling supply of the high voltage required for blowing the antifuse in accordance with a state of blowing.
In particular, supply of the high voltage applied to one of the nodes of the antifuse can be controlled in accordance with the voltage on the other node of the antifuse.
Particularly, the state of blowing of the antifuse can be tested in the program mode.
Particularly, an initial failure of the antifuse can be tested.
A semiconductor integrated circuit device according to the invention includes a plurality of memory cells; a plurality of redundant cells to be used as substitutes for defective memory cells among the plurality of memory cells; and a plurality of antifuse address detecting circuits programmable with program addresses corresponding to the defective memory cells in a program mode, and issuing a result of determination, in a read mode, by determining whether the redundant cell is used or not in response to an applied comparison address. Each of the plurality of antifuse address detecting circuits has an antifuse having a capacity type structure and being changed into a low resistance element when the capacity type structure is blown by application of a high voltage, a first node connected to one of terminals of the antifuse, a second node connected to the other terminal of the antifuse, a first supply circuit for applying the high voltage required for blowing the antifuse to the first node in the program mode, a second supply circuit for supplying a voltage to the second node, a control circuit for controlling supply of the voltage from the first supply circuit to the first node in response to the voltage on the second node, a common node for outputting the result of the determination, and a detecting circuit for determining a state of blowing of the corresponding antifuse in response to the corresponding comparison address, and charging/discharging the common node based on a result of the determination in the read mode. The semiconductor integrated circuit device further includes a select circuit being responsive to respective signals on the common nodes to select the corresponding memory cells or the corresponding redundant cells.
Accordingly, the invention further provides the following advantages. Since the program element (antifuse) which does not require blowing of a fuse with laser is used in the redundancy determining circuit, the programming steps can be reduced in number. Since the supply of the high voltage required for blowing the antifuse is controlled in accordance with the state of blowing, it is possible to prevent an influence of the high voltage on the peripheral element.
Particularly, the state of blowing of the antifuse can be tested in the program mode.
Particularly, an initial failure of the antifuse can be tested. Also, in accordance with the result of the initial failure, it is possible to disable the corresponding antifuse address detecting circuit.
Further, a bipolar transistor may be arranged in a high voltage applied region of the antifuse, whereby it is possible to prevent erroneous programming, which may be caused by serge applied during a non-programming period. A shield layer may be arranged for the antifuse, whereby an influence on peripheral elements can be prevented.
An antifuse address detecting circuit according to the invention includes a program circuit to be programmed by applying a high voltage in response to an applied program address and determining the programmed state based on an applied comparison address to output a result of the determination; and a shield layer for shielding an antifuse.
Accordingly, the invention can further provide the following advantage. Since the shield layer is provided for the antifuse which is programmed by applying the high voltage applied thereto, an influence by blowing on peripheral elements can be suppressed, and a normal operation can be ensured.
Particularly, a bipolar transistor may be arranged in a high voltage applied region of the antifuse programmable with the high voltage applied thereto, whereby erroneous programming due to serge can be prevented. A voltage on a gate region of the bipolar transistor may be externally adjusted, whereby it is possible to control a path of a current in a region of the antifuse externally supplied with the high voltage.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.